Digital Systems 4: High Speed Systems
Subject ELEN40010 (2010)
Note: This is an archived Handbook entry from 2010.
Credit Points: | 12.50 | ||||||||||||
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Level: | 4 (Undergraduate) | ||||||||||||
Dates & Locations: | This subject has the following teaching availabilities in 2010: Semester 2, Parkville - Taught on campus.
Timetable can be viewed here. For information about these dates, click here. | ||||||||||||
Time Commitment: | Contact Hours: Twenty-four hours of lectures, 12 hours of tutorials and 12 hours of laboratory and project work Total Time Commitment: 120 hours | ||||||||||||
Prerequisites: | 431-328 Digital Systems 3: Circuits and Systems | ||||||||||||
Corequisites: | None | ||||||||||||
Recommended Background Knowledge: | None | ||||||||||||
Non Allowed Subjects: | None | ||||||||||||
Core Participation Requirements: | For the purposes of considering request for Reasonable Adjustments under the Disability Standards for Education (Cwth 2005), and Students Experiencing Academic Disadvantage Policy, academic requirements for this subject are articulated in the Subject Description, Subject Objectives, Generic Skills and Assessment Requirements of this entry. The University is dedicated to provide support to those with special requirements. Further details on the disability support scheme can be found at the Disability Liaison Unit website: http://www.services.unimelb.edu.au/disability/ |
Coordinator
Assoc Prof William ShiehContact
Melbourne School of Engineering OfficeBuilding 173, Grattan Street
The University of Melbourne
VIC 3010 Australia
General telephone enquiries
+ 61 3 8344 6703
+ 61 3 8344 6507
Facsimiles
+ 61 3 9349 2182
+ 61 3 8344 7707
eng-info@unimelb.edu.au
Subject Overview: |
On completion of this subject, students should have an understanding of some advanced topics in digital system design, taken from the following. Timing in digital systems - clock distribution, including sources and management of skew; metastability and synchronisation; the effect of loading; synchronous and asynchronous bit level transport, including line coding, scrambling, clock recovery, timing requirements, jitter (sources and effect), jitter filtering and bit stuffing. Noise in digital systems - signal referencing; grounding; crosstalk; simultaneous switching; power supply distributions and related issues including impedance of parallel planes, loss and damping, impedance control over frequency, decoupling and interaction of lumped and distributed impedances. Interfacing to the analogue world - sample and hold circuits; techniques for converting between analogue and digital representations of signal; noise analysis and quantisation effects. |
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Objectives: |
On completion of this subject the student should be able to:
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Assessment: |
The relative weighting of test and/or project report will be specified both in the first lecture and on the subject web page at the start of semester. |
Prescribed Texts: | None |
Breadth Options: | This subject is not available as a breadth subject. |
Fees Information: | Subject EFTSL, Level, Discipline & Census Date |
Generic Skills: |
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Related Course(s): |
Bachelor of Engineering (Computer Engineering) Bachelor of Engineering (Computer) and Bachelor of Arts Bachelor of Engineering (Electrical Engineering) Bachelor of Engineering (Electrical) and Bachelor of Arts Bachelor of Engineering (Electrical) and Bachelor of Laws Bachelor of Engineering (Electrical) and Bachelor of Science Bachelor of Engineering (EngineeringManagement) Computer Bachelor of Engineering (EngineeringManagement) Electrical Bachelor of Engineering (IT) Computer Engineering Bachelor of Engineering (IT) Electrical Engineering Bachelor of Engineering (Mechatronics) and Bachelor of Computer Science Bachelor of Engineering (Software Engineering) Postgraduate Certificate in Engineering |
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