Note: This is an archived Handbook entry from 2015.
|Dates & Locations:|| |
This subject has the following teaching availabilities in 2015:Semester 1, Parkville - Taught on campus.
Timetable can be viewed here. For information about these dates, click here.
|Time Commitment:||Contact Hours: 1 two hour lecture per week |
Total Time Commitment:
Corequisites for this subject are:
Study Period Commencement:
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|Core Participation Requirements:||
For the purposes of considering request for Reasonable Adjustments under the Disability Standards for Education (Cwth 2005), and Students Experiencing Academic Disadvantage Policy, academic requirements for this subject are articulated in the Subject Description, Subject Objectives, Generic Skills and Assessment Requirements of this entry. The University is dedicated to provide support to those with special requirements. Further details on the disability support scheme can be found at the Disability Liaison Unit website: http://www.services.unimelb.edu.au/disability/
CoordinatorProf Stan Skafidas
Prof Stan Skafidas
Upon completion of this class, students will be able to design an analog-digital interface from system-level specifications such as input signal and disturbance characteristics. The students will learn how to design, analyse and characterise all components of an acquisition chain, including filters and A/D or D/A converters.
Principles of analog-to-digital interfaces: concepts of aggressors, noise, signal-to-noise ratio, dynamic range, resolution and accuracy. Methodology for interface design from system specifications. Filter architectures and implementations: Biquad and Ladder filters, switched capacitor and continuous-time filter; OTA-RC and opamp-RC implementation. D/A converter architectures and characterization: differential and integral non-linearity and spectral metrics; binary, thermometer and segmented architectures. A/D converter architectures: Flash, pipelined, successive approximation, oversampling converter. Analysis of error sources in A/D converter architectures and impact on design.
INTENDED LEARNING OUTCOMES (ILO)
Having completed this unit the student should be able to:
Intended Learning Outcomes (ILOs) 1-4 are assessed in the final exam, the submitted assignments, and class participation. ILOs 1, 3 and 4 are also assessed in the submitted project work.
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This subject is not available as a breadth subject.
|Fees Information:||Subject EFTSL, Level, Discipline & Census Date|
LEARNING AND TEACHING METHODS
Lecture notes and homework assignments.
INDICATIVE KEY LEARNING RESOURCES
Lecture notes, online materials, and text books.
Master of Nanoelectronic Engineering |
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