Note: This is an archived Handbook entry from 2015.
|Dates & Locations:|| |
This subject has the following teaching availabilities in 2015:Semester 2, Parkville - Taught on campus.
Timetable can be viewed here. For information about these dates, click here.
|Time Commitment:||Contact Hours: 1 two hour lecture per week |
Total Time Commitment:
Prerequisites for this subject are
Study Period Commencement:
|Recommended Background Knowledge:|| |
|Non Allowed Subjects:|| |
|Core Participation Requirements:||
For the purposes of considering request for Reasonable Adjustments under the Disability Standards for Education (Cwth 2005), and Students Experiencing Academic Disadvantage Policy, academic requirements for this subject are articulated in the Subject Description, Subject Objectives, Generic Skills and Assessment Requirements of this entry. The University is dedicated to provide support to those with special requirements. Further details on the disability support scheme can be found at the Disability Liaison Unit website: http://www.services.unimelb.edu.au/disability/
CoordinatorProf Stan Skafidas
Prof Stan Skafidas
Students will be introduced to the complete front-end to back-end semiconductor processes involved in building integrated circuits. The former includes implant and diffusion of dopants, thin-film deposition, photolithography, and metallisation. Back-end processes such as packaging, testing and ESD protection which play critical roles in the design of real chipsets and systems will also be covered. This subject will enable students to appreciate the scale and variability of semiconductor processes which ultimately determine the yield of ICs. Students will also be introduced to activities by the International Technology Roadmap for Semiconductors organization which ensures advancement in the performance of IC and related products.
Semiconductor processing, device mismatch, packaging and assembly, reliability and yield, electrostatic discharge protection circuitry
INTENDED LEARNING OUTCOMES (ILO)
Having completed this subject it is expected that the student be able to:
Intended Learning Outcomes (ILOs) 1-3 are assessed in the final exam and the submitted project report.
|Prescribed Texts:|| |
|Breadth Options:|| |
This subject is not available as a breadth subject.
|Fees Information:||Subject EFTSL, Level, Discipline & Census Date|
LEARNING AND TEACHING METHODS
Lectures and worked examples, video presentations, guest lectures
INDICATIVE KEY LEARNING RESOURCES
Students are provided with lecture slides, worked examples and reference text list
CAREERS / INDUSTRY LINKS
Exposure to cleanroom manufacturing through visits to nearby cleanroom facilities and inviting guest lectures from cleanroom lab managers.
Master of Nanoelectronic Engineering |
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