Mixed Signal Design

Subject ELEN90047 (2014)

Note: This is an archived Handbook entry from 2014.

Credit Points: 12.50
Level: 9 (Graduate/Postgraduate)
Dates & Locations:

This subject is not offered in 2014.

Time Commitment: Contact Hours: 1 two hour lecture per week
Total Time Commitment:

200 hours

Prerequisites:

None

Corequisites:

Corequisites for this subject are

Subject
Study Period Commencement:
Credit Points:
Semester 1
12.50
Recommended Background Knowledge:

None

Non Allowed Subjects:

None

Core Participation Requirements:

For the purposes of considering request for Reasonable Adjustments under the Disability Standards for Education (Cwth 2005), and Students Experiencing Academic Disadvantage Policy, academic requirements for this subject are articulated in the Subject Description, Subject Objectives, Generic Skills and Assessment Requirements of this entry. The University is dedicated to provide support to those with special requirements. Further details on the disability support scheme can be found at the Disability Liaison Unit website: http://www.services.unimelb.edu.au/disability/

Contact

Prof Stan Skafidas

Email: sskaf@unimelb.edu.au

Subject Overview:

AIMS

Upon completion of this class, students will be able to design an analog-digital interface from system-level specifications such as input signal and disturbance characteristics. The students will learn how to design, analyze and characterize all components of an acquisition chain, including filters and A/D or D/A converters.

Indicative Content:

Principles of analog-to-digital interfaces: concepts of aggressors,noise, signal-to-noise ratio, dynamic range, resolution and accuracy. Methodology for interface design from system specifications. Filter architectures and implementations: Biquad and Ladder filters, switched capacitor and continuous-time filter; OTA-RC and opamp-RC implementation. D/A converter architectures and characterization:differential and integral non-linearity and spectral metrics; binary, thermometer and segmented architectures. A/D converter architectures: Flash, pipelined, successive approximation, oversampling converter. Analysis of error sources in A/D converter architectures and impact on design.

Learning Outcomes:

INTENDED LEARNING OUTCOMES (ILO)

Having completed this unit the student should be able to:

  1. Determine the specification of critical blocks of an analog-digital interface from system/application requirements
  2. Characterize all components of an analog-digital interface (filters and A/D converters)
  3. Design and implement continuous-time and switched capacitor high-order filters
  4. Design and implement flash, pipeline, successive approximation or sigma-delta A/D converters

Assessment:
  • One written examination (not exceeding three hours) at the end of semester, worth 50%;
  • 4-6 homework assignments each 250 words equivalent over the semester, worth 20%
  • Design project, submitted project work of 1000 words per student, due at the end of semester, worth 20%
  • Class Participation, worth 10%

Intended Learning Outcomes (ILOs) 1-4 are assessed in the final exam, the submitted assignments, and class participation. ILOs 1, 3 and 4 are also assessed in the submitted project work.

Prescribed Texts:

None

Breadth Options:

This subject is not available as a breadth subject.

Fees Information: Subject EFTSL, Level, Discipline & Census Date
Generic Skills:
  • Ability to apply knowledge of science and engineering fundamentals
  • Ability to undertake problem identification, formulation, and solution
  • Ability to utilise a systems approach to complex problems and to design andoperationalperformance
  • Ability to build and test real world systems that meet industry specialisation and manufacturing standards
  • Capacity for lifelong learning and professional development
Notes:

LEARNING AND TEACHING METHODS

Lecture notes and homework assignments.

INDICATIVE KEY LEARNING RESOURCES

Lecture notes, online materials , and text books.



Related Course(s): Master of Nanoelectronic Engineering

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